1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory refreshing stored data.
2. Description of the Background Art
A ferroelectric memory (FeRAM: ferroelectric random-access memory) is generally known as an exemplary nonvolatile memory. The ferroelectric memory utilizes pseudo-capacitance change responsive to the direction of polarization of a ferroelectric substance as a memory element. The ferroelectric memory is exceedingly excellent in high data-rewriting rate and low power consumption as compared with a flash memory being a typical example of a conventional nonvolatile memory, and is expected as a next-generation nonvolatile memory.
In the ferroelectric memory, however, when leaving the ferroelectric memory, in which data is written, for a long time, a hysteresis curve is shifted in a positive or negative direction (horizontal direction), whereby an imprint, in which a quantity of polarization is gradually reduced over time, disadvantageously occurs as a characteristic of the ferroelectric substance. Therefore, when the imprint occurs, the quantity of the polarization written in the ferroelectric memory as data is reduced over time. Thus, when the quantity of the polarization is reduced to not more than a quantity necessary for reading data, the ferroelectric memory can not disadvantageously function as a memory.
Japanese Patent Laying-Open No. 10-162588 (1998) discloses a memory capable of suppressing an imprint. This memory measures time by a timer, accesses at least all memory cells in which data is written upon a lapse of a prescribed time, and writes data having an opposite polarity to the data held. Thereafter, original data is rewritten again, whereby an imprint is suppressed.
The memory disclosed in Japanese Patent Laying-Open No. 10-162588 (1998), however, must be disadvantageously provided with the timer for performing a measurement for a long time in order to measure the time of access for preventing an imprint with respect to the memory cells. Therefore, circuit size is disadvantageously increased. Additionally, the access must be performed with respect to the all memory cells each prescribed time measured by the timer. Thus, a period for an original access of the memory is disadvantageously shortened, and power consumption of the memory is disadvantageously increased.